setup and hold time with set_input_delay

It would be a really good idea to start a new thread instead of resurrecting one that is 17 years old!

For A, you are describing a source synchronous interface ("data and clock are coming from same external source") so trace delay should match between clock and data, which usually cancels them out when calculating the value for set_input_delay.  So either this statement is not correct (it's not a source synchronous design) or it is SS and very poorly routed on the board.  Can you clarify the setup and where you are getting your numbers, including Tco of the external upstream device or any provide Tsu and Th requirements?

For B, are you talking about two FPGAs sending and receiving data?  And again, is this meant to be SS or just synchronous with a common external clock source?