setup and hold time with set_input_delay

I could not locate your old documents. I have trouble with understand sset_input_delay constraint.

A) it is difference between data arrival and clock arrival time. 

assume data and clock are coming from same external source. clock period is 10ns. set_input_delay is 3. external clock signal has trace delay of 4ns.

out of the 10ns, data used up 3ns, but clock also has a delay and reaches the internal flop late by 4ns, does it not mean that data now has 11ns to meet setup time of that internal flop?

how is it even possible that difference between their arrivals is 3ns but clock trace takes 4ns?

if clock trace takes 3ns, will data have 10ns internally to travel to the flop's input?

I will subtract setup time of the internal flop. I am trying to keep numbers simple. 

B) if two chips are talking to each other then isnt set_input_deay of one chip same as set_output_delay of another chip. ? then why do I need both. 

it will be big help if you can help me solve these. I asked AI and I was able to convince it to give me the answer I wanted.