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Altera_Forum's avatar
Altera_Forum
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17 years ago

setup and hold time with set_input_delay

Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface that is connected to an FPGA. This interface has a clock (Clk) and a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Rysc, thank you kindly for your posts and clearing up IO constraints. The Quartus Documentation is extremely shotty. Thanks again.