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Altera_Forum's avatar
Altera_Forum
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17 years ago

setup and hold time with set_input_delay

Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface that is connected to an FPGA. This interface has a clock (Clk) and a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks for the reply, It indeed allows to uncheck latches for the RAM, but i'm not sure weather it also allows for CYCLONE 3 FPGA.

It indicated some error when i did,and tried to compile.