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Altera_Forum
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17 years ago

setup and hold time with set_input_delay

Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface that is connected to an FPGA. This interface has a clock (Clk) and a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

hello Everyone,

Sorry for posting question in middle of no where, I did not find how to start new thread,Ok anyways

My question is,

The LPM Ram or Ram created thr MEGAWIZARD has a input latch and an output latch, because of which we are getting the 2 cycles delay in the output, which is very crucial in our design, how to over come the delay caused by the RAM, Cant we overcome this latch, if so how do we do it.