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Altera_Forum's avatar
Altera_Forum
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17 years ago

setup and hold time with set_input_delay

Hello, I have some problem understanding the set_input_delay min and max constraint. Assume that you have an interface that is connected to an FPGA. This interface has a clock (Clk) and a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I think it just means to add the following line to your .sdc:

derive_clock_uncertainty

(That should be in all .sdc files for devices 65nms and newer...)

And note that, even though your slack is getting tight, if you meet timing, and if everything is correct, then you're in good shape. I've seen designs meet timing by a few picoseconds.