setup and hold time with set_input_delay

Thanks again Rysc for your reply.

I am fairly sure that the delay of 6.6 ns specified is the max delay between the rising edge of clock leaving the PowerPC and the time the data bits are stable. I have attached the datasheet and on page 78 these details are given. Perhaps you could have a quick look at this if you had time. On page 69 there is a timing diagram where the tov max delay term is used and it seems to refer to what I think.

Anyway I took your advice and used a PLL to shift the clock and I have been able to meet timing. I had to shift the clock by +5ns to meet timing. I now have a worst case setup time of 0.790ns and a worst case hold time slack of 2.123ns.

I have not included board trace delays in the input_delay constraints, its something I will add later, but I am assuming that they would typically quite low in the order of 100´s of ps?

I am also receiving some warnings about no clock uncertainty assignment on the clocks. From looking at the attached datasheet on page 67 it specifies the max and min high and low time for PerClk (the clock in question). The values given are that the clock can be high for between 7.5 and 9.9ns (50-66%)of a 15 ns cycle and low for between 4.95ns and 7.5 ns (33-50%) on a 15 ns cycle.

Does the potential difference in duty cycle represent clock uncertainty or am I misunderstanding clock uncertainty?

If my understanding is correct, then between the 6.6ns delay on the databus and the difference in potential duty cycle, it would make meeting timing even more difficult.

Do you have any thoughts on this?

Many Thanks