setup and hold time with set_input_delay

Thank you Rysc for your reply, things are certainly much clearer now.

I was having a read of the datasheet of the PowerPC and on the I/O specifications chapter there is a spec given for "Valid Delay Tov max" which from looking at timing diagrams seems to be the max delay between the rising clock edge and the time at which the referenced signal is stable on the putput of the PowerPC.

In the case of the databus the max delay is 6.6ns and the min 0ns.

Given that the setup relationship is 7.5 ns, it looks like this presents a problem.

Anyway I am thinking that multicycle constraints will be nessesery here. I may have to have the PowerPC configured to prolong the transfer and present the data for a longer period. eg 1 cycle more that it is currently set for. By setting placing a multicycle on the register which latches the data I should be able to succesfully meet timing.

I am resonably familiar with multicycles and from having a quick look around the forum there seem to be plenty of threads on this topic which I can study.

Really I was just wanting to know if my thinking was right on this, or indeed if there is another/better solution when this problem arises.

Many thanks for the help.