setup and hold time with set_input_delay

It's often good practice to get exact delays.

I STRONGLY recommend documenting your .sdc. You can just do comments like:

# The PPC datasheet has a clock Tco of 6-8ns from datasheet dated July 2007,

# And the board delay is 1ns +/-50ps from board layout, so adding those together...

or you can do equations in Tcl:

set ppc_max_tco 8.0 ;# PPC datasheet July 2007

set ppc_clk_max 1.05 ;# Max board delay Dave told me when doing board sims..

set max_ppc_clk [expr $ppc_max_tco + $ppc_clk_max]

That way the constraints are documented. I can't tell how many times I've seen people with a "well, the Tsu constraint is 4ns, and someone else did it and I have no idea how they came to that, but I have to meet that. And if we change the board layout I'm not sure what to do, or if we get different speed grade parts I'm not sure...."

That all being said, you have LOT of margin. Source synchronous interfaces run very fast(think 200MHz DDR, or a 400Mbps is pretty common). So you could just throw in something big. Then try to see if something's available from the datasheet, or measure it, or just say, hey that should be more than enough. Remember at one point you weren't constraining this at all, so you need to balance the amount of time it takes to get it exact(you could do HSPICE modeling and all sorts of other stuff, but if you meet timing by ns, why spend the time). If you upgrade to a faster interface, then maybe you'll want to refine it, but if it's documented how you got the numbers, you have a good starting point.