setup and hold time with set_input_delay

Thanks again Rysc for your response.

Just one further question regarding the maximum and minumun delay that should be selected.

Generally speaking what would be the approach when deciding what delays to use for the set_input_delay constraint?

Would it be analysis of the datasheet of the external device to uncover exactly what delays they may be between a clock and a data signal leaving the external device and also analysis of the respective board delays?

The problem I am having is that the exact times are not given in the PowerPC handbook as to the difference in time of the clk and data for example (although I want to check and see if more docs are available). Would the best idea be to allow for a small +/- delay here? or is it essential to uncover the exact specs.

The second issue I have is that we are still in the process of doing the board schematics but from talking to one of the guys he is not sure if whatever simulation software will provide us with the times, but I am not sure if this is the case. But I am assuming it is imperative to have an accurate idea of different trace delays? Do most designers usually obtain these times?

Basically what I am looking for is an account of anyone´s experience in doing this. Is it something that is normally done very accurately or is an exagerated delay usually placed just to cover all scenarios?

Many thanks.