setup and hold time with set_input_delay

Yes, I would say the uTsu is generally subtracted from the Data Required. That being said, I've seen cases where the models show stuff that's not really "real". For example, they may model some of the clock delay at the flip-flop, to the point that the uTsu looks positive. I've seen a few things that don't work when dissected, but for the full-analysis are correct, and imagine this to be the case. Naturally, Altera is doing less and less of this. THe fact that you noticed that is a good sign that you get what's occuring.

Note that you've basically said the data may hit the FPGA +/-1.5 from the clock. The +1.5 was just made up by me, so try to get something that reflects what's occurring.

And the fitter will try to meet your timing. In fact, that's why it's good to do both -max and -min, so it knows what the mid-point is, that gives the best slack for both setup and hold. (Since you have symmetric external delays, the mid-point is to have the clock and data paths match exactly, which makes sense from a logical perspective.)