setup and hold time with set_input_delay

Hi Rysc, thank you so much for your reply. Things are starting to become much clearer now.

Just to be doubly sure about one thing..

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So your clock coming into the FPGA(from the PPC) is:

create_clock -period 15.0 -name ppc_clk [get_ports ppc_clk]

(Naturally the port name will be different, you can give it whatever name you want, and the period might not be correct, as I wasn't sure if it was 6.6666)

The external clock is:

create_clock -period 15.0 -name ppc_ext

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The clock you refer to as external clock is a 'Virtual Clock'? which is 'simulating' the clock on the Power PC driving the data lines etc to the FPGA?

I placed the set_input_delay constraint with max delay 1.5ns and was able to analyze the resulting setup times using the report_timing command. It makes perfect sense and thank you for the explanation. There is however one thing I am not sure about. When analyzing the setup slack and viewing the data path tab, in the data_required_section the final increment is Tsu. My understanding is that this time should be subtracted from the total but it seems that it is added to the total time thus increasing the Data Required Path. Below is a snapshot of the last two stages.

10.358 0.558 FR CELL 1 FF_X34_Y1_N7 RESET_CONTROL_LOGIC:RESET_CONTROL_LOGIC_Inst|Reset_Ctrl_Reg[8]

10.376 0.018 uTsu 1 FF_X34_Y1_N7 RESET_CONTROL_LOGIC:RESET_CONTROL_LOGIC_Inst|Reset_Ctrl_Reg[8]

I placed another set_input_delay for the hold time.

set_input_delay -add_delay -min -clock [get_clocks {PPC_Virtual}] -1.500 [get_ports {PPC_GLUE_PER_DATA[0]}]

I am able to view the individual paths and it makes sense.

For the hold time constraint, I used the same value, but for example if from analyzing the trace delays on the board, the clock will always arrive 500ps before the data pins, would it always be nessesery to put a min constraint in place (and vice versa)? Or is it good practise to always leave a bit of a 'buffer' just to be sure that things aren´t too tight?

One final thing. So when I put in place the set_input_delay max and min contraints, does quartus use these only to produce the setup and hold time details, or does it take these and actively try to meet setup and hold time on each signal specified. Will the fitter make extra effort if it sees that it cannot make a setup time based on the set_input_delay constraint placed by the designer?

I am going to continue to place these contraints for each signal on this particular interface. Just to get an idea what other constraints would be required before I can say that the interface is completely constrained?

Many thanks for your help so far, things are starting to become clearer (but please put me back in my box if anything I said above is untrue!)

Reagrds,

Ardni