Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

set multicycle on derived clocks

hi, I have 2 derived clocks of a base clock which divide by 2 and 3 (for e.g). If these go to clock enables of a source and sink register, then I wish to do a multicycle on this register 2 reg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Throw it into a report_timing and see what happens, e.g.:

report_timing -setup -npaths 100 -pairs_only -from [get_fanouts {clkA}] -panel_name "Get Fanout Test"