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Altera_Forum
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13 years ago

set multicycle on derived clocks

hi, I have 2 derived clocks of a base clock which divide by 2 and 3 (for e.g). If these go to clock enables of a source and sink register, then I wish to do a multicycle on this register 2 reg...
Altera_Forum's avatar
Altera_Forum
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13 years ago

thanks rysc. My confusion on get_fanouts {CLKA} stems from the fact that

the register to register path is from Q of register 1 whose clock enable is CLKA

to D of register 2 whose clock enable is CLKB.

So I guess you are saying that the tool is smart enough to figure out that the constraint

is actually on the fanout path of register A ending on register B, even though we said

get_fanout on CLKA.