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Altera_Forum
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13 years ago

set multicycle on derived clocks

hi, I have 2 derived clocks of a base clock which divide by 2 and 3 (for e.g). If these go to clock enables of a source and sink register, then I wish to do a multicycle on this register 2 reg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi Rysc,

How will I do this if the 2 clocks are given as clock enables to the registers?

something like -from [get_fanouts {clkA}] or do I have to do more complex manipulation.

thanks.