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Altera_Forum
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13 years ago

set multicycle on derived clocks

hi, I have 2 derived clocks of a base clock which divide by 2 and 3 (for e.g). If these go to clock enables of a source and sink register, then I wish to do a multicycle on this register 2 reg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I had one case where the clocks were a strange frequency(I think 4/5ths of each other) and we couldn't do it with multicycles. Instead use

set_max_delay -from [get_clocks {clkA}] -to [get_clocks {clkB}] 4.0

Where the value is whatever setup relationship you want. This will do the exact same analysis but you're directly entering a value instead of multicycle. (I was annoyed that we couldn't achieve it with Multicycles, but this works perfectly fine)