Altera_ForumHonored Contributor12 years agoset_max_skew changed in 13.0sp1? i need to contraint a input port which is registered by for clock edge(clk0 rising, clk90 rising, clk0 falling, clk90 falling). i have done these using set_max_skew in v9.1 quartus with cyclone2 ....Show More
Altera_ForumHonored Contributor12 years agoand if i report exclude from_clock to_clock . skew would be fine
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