Set_input_delay misunderstanding

Hi Rysc and kaz;

My obvious mistake was the syntax error caught by kaz on the "-" in front of the timing delay. Once I fixed this, my hold time violation went away. I did try using a virtual clock and the slack results were almost the same. In either case through the different discussions in this thread, I have learned a lot .

Rysc :

a) you have described the case where the FPGA sends the clk to an external register and how you setup your. If the clock and data are generated by the external device (asynchronous to any clock on the FPGA) , how will the constrains set_input_delay,set_output_delay change assuming the spec from the Ext device give you tCo min max for data respect clk

tH min for data respect to clk

thank you

thanks