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Altera_Forum
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12 years ago

Set_input_delay misunderstanding

Hello: new to sdc constrains I have 2 cases to constrain my serial data coming in and trying to understand the differences Case 1 has been done in previous projects right or wrong b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Hold violations are restricted Fmax? I haven't seen this, but not sure how it would work. A hold violation within a domain basically means it can't run at any rate, i.e. even 1 Hz. So not sure how it would show the magnitude of failure without a negative number or something strange like that.

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Rysc please look here:

http://quartushelp.altera.com/11.1/mergedprojects/tafs/tafs/tcl_pkg_sta_ver_1.0_cmd_get_clock_fmax_info.htm

I will leave you guessing what this type of hold violation actually is...