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AhmadZaklouta's avatar
AhmadZaklouta
Icon for New Contributor rankNew Contributor
4 years ago

set false path in VHDL

I want to write sdc constraint for two signals in VHDL but I am not being able to understand the syntax. the signals are term_count_internal and time_cnt_wrap_dly this what I tried but it wrong:...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.