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AhmadZaklouta's avatar
AhmadZaklouta
Icon for New Contributor rankNew Contributor
4 years ago

set false path in VHDL

I want to write sdc constraint for two signals in VHDL but I am not being able to understand the syntax. the signals are term_count_internal and time_cnt_wrap_dly this what I tried but it wrong:...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Ahmad,


Below are the syntax for altera_attribute package regarding the package for making assignments. Few restrictions of the implication which you can refer in below link for more details.


https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_attribute.htm


Quartus only supports altera_attribute on entities, instances, ports, and registers. If applied to any other object, the synthesis attribute is ignored.