Forum Discussion
AhmadZaklouta
New Contributor
New Contributorset false path in VHDL
I want to write sdc constraint for two signals in VHDL but I am not being able to understand the syntax.
the signals are term_count_internal and time_cnt_wrap_dly
this what I tried but it wrong:...
SyafieqS
Super Contributor
Super ContributorAhmad,
May I know what Quartus version are you using? Std,Pro?
If Std, there might be some limitation in term of HDL construct and support thus prevent you from to do so.
AhmadZakloutaNew Contributor
New ContributorQuartus prime pro 21.4
