Forum Discussion
AhmadZaklouta
New Contributor
New Contributorset false path in VHDL
I want to write sdc constraint for two signals in VHDL but I am not being able to understand the syntax.
the signals are term_count_internal and time_cnt_wrap_dly
this what I tried but it wrong:...
sstrell
Super Contributor
Super ContributorNo offense, but is there a reason why you don't just use a separate .sdc file? It will make your life much easier.
AhmadZakloutaWe are designing a library that is used accros multiple projects. so we don't have to write constraint for each project when it is embedded in the rtl.
