Forum Discussion

AhmadZaklouta's avatar
AhmadZaklouta
Icon for New Contributor rankNew Contributor
4 years ago

set false path in VHDL

I want to write sdc constraint for two signals in VHDL but I am not being able to understand the syntax. the signals are term_count_internal and time_cnt_wrap_dly this what I tried but it wrong:...
AhmadZaklouta's avatar
AhmadZaklouta
Icon for New Contributor rankNew Contributor
4 years ago

The VHDL syntax is not clear!
I have tried all these and non work:

attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers *time_cnt_wrap_dly*]"";""-name SDC_STATEMENT ""set_false_path -from [get_registers *term_count_internal*]""";
attribute altera_attribute of rtl : architecture is (
"-name SDC_STATEMENT ""set_false_path -to [get_registers *time_cnt_wrap_dly*]"";" &
"-name SDC_STATEMENT ""set_false_path -from [get_registers *term_count_internal*]""
);
attribute altera_attribute of rtl : architecture is 
"-name SDC_STATEMENT ""set_false_path -to [get_registers *time_cnt_wrap_dly*]"";" &
"-name SDC_STATEMENT ""set_false_path -from [get_registers *term_count_internal*]""";