Forum Discussion
AhmadZaklouta
New Contributor
New Contributorset false path in VHDL
I want to write sdc constraint for two signals in VHDL but I am not being able to understand the syntax.
the signals are term_count_internal and time_cnt_wrap_dly
this what I tried but it wrong:...
sstrell
Super Contributor
Super ContributorThis seems to explain what you need to do to do this:
AhmadZakloutaI read this but I want to have two set_false_path for two different signal and I am not being able to figure out the syntax.
