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Altera_Forum's avatar
Altera_Forum
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8 years ago

set design clock

Hi All, I have hard time trying to create clock based process in Verilog. I am using mini board with EP2C5T144C8 chip. I rote a simple code ad checking output signals with scope. I assign clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Why the 2nd always block works is coz, its no longer a clocked sequential block, but a combinational block. The output follows the input whenever there's a change in the input.

Try with a clock and reset, and also as Cris72 mentioned, check Pin assignments, use [15:0] instead of integers. Try the following code and check: 


module encoder (
                clock,
                reset,  // Its good to use a reset so that Flops are set to a known state.
                enc_out
                );
input  clock;
input  reset;
output enc_out;
reg enc_out;
reg  count;
always @(posedge clock or negedge reset) begin
  if(!reset) begin
     count   <= 16'd0;
  end
  else begin
     count <= count + 16'd1;
  end
end
always @ (count) begin
  if (count ==16'd50000)
        enc_out <= 1'b0;
  else if (count < 16'd25000)
        enc_out <= 1'b1;
  else
        enc_out <= 1'b0;
end
endmodule