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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

set design clock

Hi All, I have hard time trying to create clock based process in Verilog. I am using mini board with EP2C5T144C8 chip. I rote a simple code ad checking output signals with scope. I assign clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thank Cris72,

I tryed this and it doesn't help. Its even worse.

this code is working - I see on scope enc_out following end_inp:

always @(enc_inp)//posedge CLK)

begin

enc_out<=enc_inp;

end

but this one not:

always @(posedge CLK)

begin

enc_out<=enc_inp;

end

I am lost....