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Altera_Forum's avatar
Altera_Forum
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8 years ago

set design clock

Hi All, I have hard time trying to create clock based process in Verilog. I am using mini board with EP2C5T144C8 chip. I rote a simple code ad checking output signals with scope. I assign clo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Do not use integer type. Use a register instead.

reg [15:0] cnt;

then in the clock process you must make some changes, like:

cnt <= cnt + 16'd1;