Forum Discussion
Altera_Forum
Honored Contributor
12 years agoIf its one clock behind where it should be, then its just a pipelining problem. Add an extra register in the other, parrallel data path and everything is aligned again.
If its one clock behind where it should be, then its just a pipelining problem. Add an extra register in the other, parrallel data path and everything is aligned again.