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There is only one way and is surest securest: sample the pulse on the clock edge and use same clock edge as that generated it
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ie.
signal ip_r : std_logic;
process(clk)
begin
if rising_edge(clk) then
ip_r <= ip;
if ip_r = '0' and ip = '1' then
--action on rising edge
elsif ip_r = '1' and ip = '0' then
--action on falling edge
end if;
end if;
end process;
Assuming there are no timing failures this will ALWAYS work.
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If sampling fails and the clock edge did not see the pulse then either timing is not right or else your logic is not right. We trust the technology otherwise we wouldn't be here.
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Timequest will tell you if theres a timing problem
A good testbench will tell you if theres a logic problem.
Fixing either is usually acheived through modifying the code. Fixing timing problems with extra SDC constraints should be the last resort.
Honored Contributor
