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No, Start_IN is generated by core1 (called Start_OUT, obviously an OUTput). Then no logic, directly connected to core2 where it is called Start_IN (an INput).
Where do you see Start_IN giong into core1? Where do you see "some logic"?
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if you are just generating start_in from same one clock then it is ok and there is no need to consider clock crossing. Moreover this is only a register generating a pulse rather than a core (which gives impression of loads of logic). You haven't explained how do you actually generate the pulse and is it based on async reset. If it all synchronous then this pulse will not be missed in a state machine that runs on same clock unless your state machine logic is not right or timing is not right. The best thing is to show the whole code of state machine.
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