Thank you for your answer.
As you mentioned, I solved the cygwin problem. As a result, the cygwin error message in the above error message has been resolved.
However, there was still a problem downloading the elf file to the board.
but, I solved the problem as follows.
As you know, to use SDRAM, phase adjustment is required through PLL.
I set it up the same way as the tutorial, but the problem still occurred.
However, I declared two PLLs, one of which was inserted into Nios ii’s clk without changing the phase, and the other was given clk to SDRAM by changing the phase as before.
As a result, I was able to download the elf file to my DE2 board.
I still don’t know exactly why it was resolved.
However, I think that clock skew problem was solved through PLL and I was able to download it.”
If people using Quartus 13.0 version see this answer, I would like to add the following information. If a cygwin error occurs, please refer to ftp://ftp.intel.com/Pub/fpgaup/pub/Cygwin_Patch/.
Your answer was really helpful.