Honored ContributorHi there,
I'm having problem to run this sdram 48LC4M32B2-7 with my Cyclone III. If I select run on-chip then it's ok, but I run on sdram then I got error. 1. Run on-chip, I'm be able to write/read on sdram from nios 2. If I select sdram to run program, then I get USB error. Is there maybe Pll select in SOPC or something? Does anybody run into this problem before? Thanks, Sean
Honored ContributorMaybe there is a timing problem?
If timing is not 100% ok on the SDRAM, you may get errors erratically. Have you successfully run the memtest-template? Whats your result of the timing analyser? Can you give a bit more details about you system (components used, frequency).Honored ContributorThanks.
I'm using Cyclone III EP3C80F484 with this Micron MT48LC4M32B2-7. I think the phase shift. I try some -3.5ns from Stratix II, -72deg, -90deg SeanHonored Contributorone more. Hope someone point me to the right phase shift clock setting...
Best regards, SeanHonored ContributorSo, from the pictures I assume you are running both CPU and SDRAM with 100MHz, using the altera-provided SDRAM-controller?
When you compile the hardware, what is the result of the timing analysis? Any red warnings? You are right, most probably it's the clock shift. For my 100MHz-system I have to use some 306°, but it depends from the constraints defined in my .SDC file (I'm using timequest to determine setup/hold slack to be about the same size).
