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You are sure that the delay_min should be 4?
And not -4??
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I looked again into this thread and say “No I am not sure now that I have put the figures right but Rbugalho in his very last post corrected me, thanks“
The original info for FPGA outputs to the Switch is given as
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FPGA input rx and tx clock from switch device is 25 mhz. Switch device specs for its receive data lines a min setup time of 10 ns and min hold time of 0 secs on the rising clock edge.
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If clock and data are both from FPGA and assuming they arrive together then:
set_output_delay -max +tSU (i.e. 10)
set_output_delay-min –tH (i.e. -0)
That model (model 1) is based on TimeQuest docs directly.
If clock is opposite data then the beloved TimeQuest doesn’t say anything about how to constrain this destination synchronous model (model 2) but surely above equations wouldn’t apply anymore.
So I posted my initial thoughts but I could be wrong and it will help us discussing this model 2.
Let me convert model 2 to model 1 equivalent (by imagining board delay difference of data/clock).
let clock arrive (x) ns from switch and let data travel (y) ns to arrive at Switch together with our virtual clock.
What this means at FPGA (as imaginary model 1) clock delay is (–x) ns, then it launches data from FPGA, after that clock delays further (x) ns to reach Switch
So clock delay = -x+x = zero if it was model 1
Data delay = y ns
Applying model 1 equations now:
max = required tSU + data board delay – clock board delay = 10 + y - 0
min = -reqiured tH + data board delay – clock board delay = -0 + y – 0
If y = 2 ns then obviously max becomes 12, min becomes +2
So my new model gave me some difference with max value which Rbugalho corrected. I am always on the learning curve and is not always upwards.
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