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inputs to fpga:
your interpretation of 18/28 ns is not right and you need to follow tCO min as 18 ns, tCO max as 28 ns (as Rbugalho first thought).
set_input_delay -max 28
set_input_delay -min 18
since clock and data arrive with same delay then you can ignore board effect for above.
outputs:
Your output assignments are correct if clock and data arrive at same time but since your clock is opposite that of data then clock arrives late by say 2ns and data arrives after 2 ns at target switch thus you got 4 ns net delay of data relative to clock at switch. treat this as board delay so advance data by 4 ns.
set_output_delay -max 6
set_output_delay -min -(-4) i.e. 4
alternatively use virtual clock and keep your figures.
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You are sure that the delay_min should be 4?
And not -4??
Honored Contributor
