SDC set_input_delay and set_output_delay constraints

Thanks kaz and rbugalho for your responses.

The device is a KSZ8995MAI ethernet switch. I have attached a snapshot of the timing info from the datasheet. The datasheet provides an "output valid" parameter for the data lines that the switch sends data to the fpga on; this is spec'd as a min of 18 ns and max of 28 ns.

Below is what I have in my SDC file so far (updated based on your feedback). Based on the attached info, does this seem correct?

I have not factored in board delay yet, but I would expect no more than 2 ns based on my board design. Since the clock and data originate from the switch, if we assume trace lines are the same length, I wouldn't need to constrain anything on the FPGA's receive data lines, correct?

Note that mii_mrxd and mii_mtxd are data signals defined in my design.

create_clock -name {mii_txclk_25mhz_in} -period 40.000 -waveform { 0.000 20.000 } [get_ports {mii_mtxclk}]

create_clock -name {mii_rxclk_25mhz_in} -period 40.000 -waveform { 0.000 20.000 } [get_ports {mii_mrxclk}]

set_input_delay -max -clock [get_clocks {mii_rxclk_25mhz}] 28 [get_ports {mii_mrxd

[*]}]

set_input_delay -min -clock [get_clocks {mii_rxclk_25mhz}] -12 [get_ports {mii_mrxd

[*]}]

set_output_delay -max -clock [get_clocks {mii_txclk_25mhz}] 10 [get_ports {mii_mtxd

[*]}]

set_output_delay -min -clock [get_clocks {mii_txclk_25mhz}] 0 [get_ports {mii_mtxd

[*]}]

Thanks in advance