SDC set_input_delay and set_output_delay constraints

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kaz,

I think you got it wrong.

18~28 ns the window is NOT the valid window. The valid window is up to 18 ns (for hold) and from 28 ns (for setup)

So, the basic constrains are something like this

create_clock -name rx_clock -period 40 [get_ports rx_clock]

create_clock -name rx_clock_virtual -period 40

create_clock -name tx_clock -period 40 [get_ports rx_clock]

create_clock -name tx_clock_virtual -period 40

set_input_delay -min $tCO_min -clock rx_clock_virtual ...

set_input_delay -max $tCO_max -clock rx_clock_virtual ...

set_output_delay -min -$tH -clock tx_clock_virtual ...

set_output_delay -max $tSU -clock tx_clock_virtual ...

You may want to account for PCB delays on a) your clock lines and b) your data lines.

For a), you can use set_clock_latency, set_clock_uncertainty or just mix it into the input/output delay values

For b), better mix it into the input/output delay values

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Thanks Rbugalho:the OP has worded it as:

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output data will be valid a min of 18 ns and max of 28 ns after the rising clock edge

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Do you interpret that as valid after 10ns(min) and up to after 28 ns(max)?

then min tCO is 18 and max tCO is 28 ns. Fair enough if you know about their device. Thus they should set input delay to 18 min and 28 max