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Hello,
I'm new to TimeQuest / SDC commands. In my design I've got an external Ethernet switch device that is sourcing a dedicated clock signal to drive data into an FPGA. The switch device also sources a dedicated clock to read data from the FPGA. I'm trying to apply constrains for both the tx and rx data paths. I've read through the a document referenced here (TimeQuest User Guide by Ryan Scoville) along with other Altera documentation and it's not clear to me how to do this.
Maybe the first question is, can I consider this to be a source synchronous interface? The descriptions I've read on this seem to indicate that a source synchronous interface is when a clock input to the FPGA a) drives logic associated with an external device, and b) the input clock is also driven back out of the FPGA to clock the external device.
In my design, the clock is coming from the external device and the FPGA is not driving the clock back out.
Details of the clocks and setup/hold times are as follows. FPGA input rx and tx clock from switch device is 25 mhz. Switch device specs for its receive data lines a min setup time of 10 ns and min hold time of 0 secs on the rising clock edge. The switch specs for its transmit data lines that the output data will be valid a min of 18 ns and max of 28 ns after the rising clock edge.
Can anyone provide any insight into how I can constrain this?
Thanks in advance
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Your inputs to fpga(data and clock from switch) is a typical source synchronous case.
since the valid window is 18~28 ns then you need to inform timequest about the data/clock offset using set input delay as follows:
set_input_delay -max 18
set_input_delay -min -(period - 28) i.e. -12
Your outputs from fpga(data) to switch is close to source synchronous case but your clock is opposite data direction.
if it was same direction then you set max output delay to tSU i.e. 10 and min output delay to -tH i.e. 0
as your clock is not you can either estimate the effect and adjust above or use virtual clock offset(advanced) from actual clock by estimated delay.
edit: for simplicity assume data and clock have same delay across board(if input to fpga) or equal but opposite delay for outputs.
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