SDC File rules for Synchronizers

And to continue

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When using the Intel Quartus Prime Timing Analyzer with a design that contains a

DCFIFO block apply the following false paths to avoid timing failures in the

synchronization registers:

• For paths crossing from the write into the read domain, apply a false path

assignment between the delayed_wrptr_g and rs_dgwp registers:

set_false_path -from [get_registers

{*dcfifo*delayed_wrptr_g

[*]}] -to [get_registers

{*dcfifo*rs_dgwp*}]

• For paths crossing from the read into the write domain, apply a false path

assignment between the rdptr_g and ws_dgrp registers:

set_false_path -from [get_registers {*dcfifo*rdptr_g

[*]}] -to

[get_registers {*dcfifo*ws_dgrp*}]

The false path assignments are automatically added through the HDL-embedded

Synopsis design constraint (SDC) commands when you compile your design. The

related message is shown under the Timing Analyzer report.

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