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Altera_Forum
Honored Contributor
7 years agoI think for older families, and maybe older versions, Im fairly certain it was a false path - and false paths/clock groups have priority over anything else. At least this is what you got if you instantiated the DC FIFO yourself and didn't use the megawizard/IP catalog.
For newer families they added to ability to use a max delay over a false path, probably because false paths are falling out of favour for max_delays and people were probably complaining they couldn't override the embedded constraints. Maybe DC fifo got this ability too. From the DCFIFO User Guide 18.0, Page 21: --- Quote Start --- Generate SDC File and disable embedded timing constraint (29)(30) Allows you to bypass embedded timing constraints that uses set_false_path in the synchronization registers. A user configurable SDC file is generated automatically when DCFIFO is instantiated from the IP Catalog. New timing constraints consist of set_net_delay, set_max_skew, set_min_delay and set_max_delay are used to constraint the design properly. --- Quote End ---