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If you use the Altera DC fifo, they already contain an embedded false path constraint across the Clock Domain.
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Actually there is some ambiguity here.
Altera dc fifo sdc does not include false path but max delay. Here is an example:
proc apply_sdc_dcfifo {hier_path} {# gray_rdptr
apply_sdc_dcfifo_rdptr $hier_path# gray_wrptr
apply_sdc_dcfifo_wrptr $hier_path
}# # common constraint setting proc#
proc apply_sdc_dcfifo_for_ptrs {from_node_list to_node_list} {# control skew for bits
set_max_skew -from $from_node_list -to $to_node_list -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.8# path delay (exception for net delay)
if { ! } {
set_net_delay -from $from_node_list -to $to_node_list -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
}# relax setup and hold calculation
set_max_delay -from $from_node_list -to $to_node_list 100
set_min_delay -from $from_node_list -to $to_node_list -100
}# # mstable propgation delay#
proc apply_sdc_dcfifo_mstable_delay {from_node_list to_node_list} {# mstable delay
if { ! } {
set_net_delay -from $from_node_list -to $to_node_list -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
}
}# # rdptr constraints#
proc apply_sdc_dcfifo_rdptr {hier_path} {# get from and to list
set from_node_list
set to_node_list
apply_sdc_dcfifo_for_ptrs $from_node_list $to_node_list# mstable
set from_node_mstable_list
set to_node_mstable_list
apply_sdc_dcfifo_mstable_delay $from_node_mstable_list $to_node_mstable_list
}# # wrptr constraints#
proc apply_sdc_dcfifo_wrptr {hier_path} {# control skew for bits
set from_node_list
set to_node_list
apply_sdc_dcfifo_for_ptrs $from_node_list $to_node_list# mstable
set from_node_mstable_list
set to_node_mstable_list
apply_sdc_dcfifo_mstable_delay $from_node_mstable_list $to_node_mstable_list
}
This raises question for set_clock_groups as it may (or not) override this sdc. I don't have answer here as I don't know how priorities work with TimeQuest
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