Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

SDC File for Multi rate Filter

Hallo I am designing a multi-rate filter block. My input signal is 44.1 kHz and output signal is 11.2 MHz. I have designed an I2S slave receiver to get the input and then pass it through my two...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Yes i have checked it. there is no timing violation. All the paths are constrained and i have positive slack.