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With regards to your original question here, the answer is neither. You should be adding a virtual clock constraint to define the external clock that is driving the upstream device that is providing signal_x to the FPGA. A virtual clock is created with create_clock and no target because it never actually enters the FPGA device. So it might look something like this (the numbers are just examples):
create_clock -name clock_virtual -period 10.0
create_clock -name clock_x -period 10.0 [get_ports {clock_x}]
derive_pll_clocks
set_input_delay -max 5 -clock clock_virtual [get_ports {signal_x}]
set_input_delay -min 1 -clock clock_virtual [get_ports {signal_x}]
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Then, do you consider clock_virtual as being asynchronous to clock_x? My question is about setting the clock groups with the set_clock_groups command.
Honored Contributor
