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Honored Contributor
Honored ContributorSDC - What clock should the input pin be relative to?
Hello, signal_x in an input pin to my FPGA. signal_x is synchronous to clock_x which is also an input pin. clock_x drives a pll input and becomes pll_clock_x. pll_clock_x is pha...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I recompiled and ran it with the PLL set to source synchronous mode. Unfortunately, the problem persists almost no change in the negative slack. The relationship is 5.000 --- Quote End --- setup relationship must be 25 (and hold relationship should be zero). If it is 5 it will never pass. probably you are mistaken on this. Are you using different clock edges between sdc clock waveform and latching of input register. The chip planner shows the nodes are too far. use fast input registers and not fabric registers
