"scfifo_component : scfifo" is not bound

Hi,

I would like to know how to fix the binding problem of scfifo in modelsim (6.5b). I already added the altera_mf library but still the warning comes out ("scfifo_component : scfifo" is not bound) when I try to start the simulation.

altera_mf is a correct library for scfifo?

I found out that there is a mismatch in ports between the generated fifo.vhd and the scfifo of altera_mf_components.vhd

(ex. sclr, aclr ports)

What libary should I use?

Generated fifo file (using Quartus 10.1) Component mapping:

scfifo_component : scfifo

GENERIC MAP (

add_ram_output_register => "ON",

almost_full_value => 64,

intended_device_family => "Cyclone IV GX",

lpm_numwords => 128,

lpm_showahead => "OFF",

lpm_type => "scfifo",

lpm_width => 83,

lpm_widthu => 7,

overflow_checking => "ON",

underflow_checking => "ON",

use_eab => "ON"

)

PORT MAP (

clock => clock,

sclr => sclr,

wrreq => wrreq,

aclr => aclr,

data => data,

rdreq => rdreq,

empty => sub_wire0,

full => sub_wire1,

q => sub_wire2,

almost_full => sub_wire3

);

altera_mf_components.vhd (from Quartus 10.1 installed directory)

Component mapping:

component scfifo

generic (

add_ram_output_register : string := "OFF";

allow_rwcycle_when_full : string := "OFF";

almost_empty_value : natural := 0;

almost_full_value : natural := 0;

intended_device_family : string := "unused";

lpm_numwords : natural;

lpm_showahead : string := "OFF";

lpm_width : natural;

lpm_widthu : natural := 1;

overflow_checking : string := "ON";

underflow_checking : string := "ON";

use_eab : string := "ON";

lpm_hint : string := "UNUSED";

lpm_type : string := "scfifo"

);

port(

aclr : in std_logic := '0';

almost_empty : out std_logic;

almost_full : out std_logic;

clock : in std_logic;

data : in std_logic_vector(lpm_width-1 downto 0);

empty : out std_logic;

full : out std_logic;

q : out std_logic_vector(lpm_width-1 downto 0);

rdreq : in std_logic;

sclr : in std_logic := '0';

usedw : out std_logic_vector(lpm_widthu-1 downto 0);

wrreq : in std_logic

);

end component;

Thank you.