Same VHDL block RAM inferring file, different results

One possible issue is that 160 is not a power of 2 and does not match your address bit width. The VHDL template in Quartus 16.1 seems to require that and the tool may get confused otherwise. But you say it worked before. The template also uses a natural with the proper range (0 to 255 in your case) instead of an integer.

Also, under "Settings => Compiler Setting => Advanced Settings", you might want to make sure "Allow Any RAM Size for Regognition" is ON.

In the case of ROM, you have to make sure "Assignments -> Device ... -> Device and Pin Options ... -> Configuration Mode" is set to:

"Single Uncompressed Image with Memory Initialization ..."

I doubt if that would affect RAM though.

As sstrell mentions, you could use the Megawizard. The problem with wizards is they produce unmaintainable code. If you ever change something, you have to generate a wizard in parallel. Unfortunately, the Microsoft "everything should be a wizard" philosophy has infected the entire software world.

But there is a compromise solution that I tend to use. Generate the IP once using the wizard and then create a package with generics for the items of interest from the VHDL code generated by the wizard. For example, I have a dual-port RAM in my own code that looks like below. The entity is created by the wizard and I replace the hardwired numbers of the original with generics. It's not good for ROM, but for everything else it is MUCH easier than trying to deal with persnickety inference tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package timeslot_table_comp is
	component timeslot_table is
	
		generic (
			ADDR_BITS_A : natural := 10;
			ADDR_BITS_B : natural := 10;
			WIDTH_A     : natural := 32;
			WIDTH_B     : natural := 32
			);
		PORT (
			address_a : IN unsigned (ADDR_BITS_A - 1 DOWNTO 0);
			address_b : IN unsigned (ADDR_BITS_B - 1 DOWNTO 0);
			clock     : IN STD_LOGIC  := '1';
			data_a    : IN STD_LOGIC_VECTOR (WIDTH_A - 1 DOWNTO 0);
			data_b    : IN STD_LOGIC_VECTOR (WIDTH_B - 1 DOWNTO 0);
			rden_a    : IN STD_LOGIC  := '1';
			rden_b    : IN STD_LOGIC  := '1';
			wren_a    : IN STD_LOGIC  := '0';
			wren_b    : IN STD_LOGIC  := '0';
			q_a       : OUT STD_LOGIC_VECTOR (WIDTH_A - 1 DOWNTO 0);
			q_b       : OUT unsigned (WIDTH_B - 1 DOWNTO 0)
		   );
		
		
	
	end component;
end timeslot_table_comp;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use WORK.TIMESLOT_TABLE_COMP.ALL;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY timeslot_table IS
		generic (
			ADDR_BITS_A : natural := 10;
			ADDR_BITS_B : natural := 10;
			WIDTH_A     : natural := 32;
			WIDTH_B     : natural := 32
			);
		PORT (
			address_a : IN unsigned (ADDR_BITS_A - 1 DOWNTO 0);
			address_b : IN unsigned (ADDR_BITS_B - 1 DOWNTO 0);
			clock     : IN STD_LOGIC  := '1';
			data_a    : IN STD_LOGIC_VECTOR (WIDTH_A - 1 DOWNTO 0);
			data_b    : IN STD_LOGIC_VECTOR (WIDTH_B - 1 DOWNTO 0);
			rden_a    : IN STD_LOGIC  := '1';
			rden_b    : IN STD_LOGIC  := '1';
			wren_a    : IN STD_LOGIC  := '0';
			wren_b    : IN STD_LOGIC  := '0';
			q_a       : OUT STD_LOGIC_VECTOR (WIDTH_A - 1 DOWNTO 0);
			q_b       : OUT unsigned (WIDTH_B - 1 DOWNTO 0)
		   );
END timeslot_table;
ARCHITECTURE SYN OF timeslot_table IS
	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
	q_a    <= sub_wire0(WIDTH_A - 1 DOWNTO 0);
	q_b    <= unsigned(sub_wire1(WIDTH_B - 1 DOWNTO 0));
	altsyncram_component : altsyncram
	GENERIC MAP (
		address_reg_b => "CLOCK0",
		clock_enable_input_a => "BYPASS",
		clock_enable_input_b => "BYPASS",
		clock_enable_output_a => "BYPASS",
		clock_enable_output_b => "BYPASS",
		indata_reg_b => "CLOCK0",
		intended_device_family => "MAX 10",
		lpm_type => "altsyncram",
		numwords_a => 2**ADDR_BITS_A,
		numwords_b => 2**ADDR_BITS_B,
		operation_mode => "BIDIR_DUAL_PORT",
		outdata_aclr_a => "NONE",
		outdata_aclr_b => "NONE",
		outdata_reg_a => "UNREGISTERED",
		outdata_reg_b => "UNREGISTERED",
		power_up_uninitialized => "FALSE",
		read_during_write_mode_mixed_ports => "DONT_CARE",
		read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
		read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
		widthad_a => ADDR_BITS_A,
		widthad_b => ADDR_BITS_B,
		width_a => WIDTH_A,
		width_b => WIDTH_B,
		width_byteena_a => 1,
		width_byteena_b => 1,
		wrcontrol_wraddress_reg_b => "CLOCK0"
	)
	PORT MAP (
		address_a => std_logic_vector(address_a),
		address_b => std_logic_vector(address_b),
		clock0 => clock,
		data_a => data_a,
		data_b => data_b,
		rden_a => rden_a,
		rden_b => rden_b,
		wren_a => wren_a,
		wren_b => wren_b,
		q_a => sub_wire0,
		q_b => sub_wire1
	);
END SYN;