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King22's avatar
King22
Icon for New Contributor rankNew Contributor
3 years ago

s10 fpll can't lock in quartus 22.4

Hi All I use s10 fpga , and the compiler is quartus22.4 , in my design , I use a fpll as transceiver pll , but the fpll can not lock ， but when I use quartus21.1 to compile , fpll get lock...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

I found the problem to be related to cascading of the IOPLL to the FPLL. For the S10 devices, this arrangement is not allowed. Please refer to the documentation links below:

https://www.intel.com/content/www/us/en/docs/programmable/683621/current/fpll.html


https://www.intel.com/content/www/us/en/docs/programmable/683621/current/pll-cascading-clock-network.html


This is also clearly visible from the RTL Netlist Viewer against Technology Map Viewer. The RTL viewer is the logic that you intend, whereas the Technology Map viewer is the design that you get.


Regards



  • King22's avatar
    King22
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Ash_R

    So transceiver fpll (FPLL1) can use another cascade fpll (FPLL2) as reference source ,

    if this is true , Can FPLL2 's reference clock source from IOPLL like below,

    　　IOPLL-> FPLL2->FPLL1->Tranceiver

    In my real design , IOPLL will change , so I wish when IOPLL change ,

    the transceiver output data rate will auto changed also.

    Regards

    King22