Forum Discussion
GDeXi
Occasional Contributor
6 years agoS10 EMIF IP Error Report
My EMIF is set to ping-pong PHY, because the device contains two teams of CK, CKE, cs_n, ODT, but in the plan stage, such errors are always reported: Error(18612): READDATAVALID signal for sec...
Deshi_Intel
Regular Contributor
6 years agoHI,
Just to confirm are you generating example design with ping pong phy enabled ?
if yes, then that's the best reference for you to debug issue
I know it's tough and tedious but you just need to slowly compare and find out what's the difference between your design and example design.
Alternately, you can also try modify the working example design to remove traffic generator and add in your custom design to see whether it works or not to slowly figure out the problem
- I doubt it's DDR4 IP setting issue. You can try focus to check on the design connection first
- second thing is to check whether you set some weird setting in qsf file that may somehow caused the trouble
Good Luck !
Regards,
dlim
- GDeXi6 years ago
Occasional Contributor
Hi
Thank you very much . I used to do Xilinx FPGA . So I don't Know Intel FPGA Characteristic and Quartus. Sorry I'm in trouble for you