S-parameter model of the power delivery network in Quartus functional simulation

Thank you ak6dn for the detailed explanation. I am using a Cyclone IV on an evaluation board, and my dynamic power consumption was so high that a few times it reset the FPGA, so I had to reprogram it. Now it does not reset the FPGA. I am now trying to quantify the clock jitter and the propagation delay variation with self-generated supply noise. I come from an IC design background so I tend to think from the circuit perspective. Thank you for the info on "set_clock_uncertainty" feature. Is it a similar feature for signal path delay?