running design example on altera

hi sir/madam,

thank you so much for your reply.

am trying to run web server design example, there as soon as i launch sopc builder its not asking for create new system instead its showing open system and am encountering errors related to sd_ram_controller. if i disable that then there will not be any errors, it generates files. but while running those files am getting many errors.

my question is

can i disable components which are already defined?

and files generated are are in Verilog HDL files i want VHDL files

how to get VHDL files?

any suggestions are appreciated

thank you. . .